[Milkymist-devel] Event-related troubles with Icarus Verilog

Sebastien Bourdeauducq sebastien.bourdeauducq at lekernel.net
Mon Nov 26 16:06:33 CET 2012


Hi,

Consider the following Verilog source:

============
module event_test();

reg foo, bar;

always @(*) begin
	$display("bar=%d", bar);
	bar <= 1'b0;
	if(foo)
		bar <= 1'b1;
end

initial begin
	foo <= 1'd1;
	#1 $display("End of simulation - bar=%d", bar);
end

endmodule
============

The intended functionality of the always block is pretty clear: it should be a 
pass-through from "foo" to "bar" that displays the value of "bar" just before 
it changes. This corresponds to the behaviour observed when simulating with 
GPL Cver and Xilinx ISim:
bar=x
End of simulation - bar=1

But Icarus Verilog seems to take the event-driven model of Verilog a bit too 
strictly and goes into an infinite loop:
bar=x
bar=1
bar=1
bar=1
...

I'm pretty sure this is an Icarus Verilog bug, especially since rewriting the 
always block in this way fixes the problem:
============
always @(*) begin
	$display("bar=%d", bar);
	if(foo)
		bar <= 1'b1;
	else
		bar <= 1'b0;
end
============

Anyone with a Modelsim install wants to see what it does?

I'm posting it here since this sort of issue tends to pop up when simulating 
Migen-built Verilog, as Migen is quite zealous when initializing signals in 
combinatorial always blocks.

Sebastien



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